Non-volatile electrically erasable integrated circuit memory devices may be categorized as EEPROMs and flash EPROMs (sometimes also called flash EEPROMs). EEPROMs utilize the wellknown Fowler-Nordheim tunneling mechanism for both programming and erase. In contrast, flash EPROMs utilize hot-electron injection for programming and Fowler-Nordheim tunneling for erase.
U.S. Pat. No. 4,203,158, discloses a typical EEPROM floating gate cell based on Fowler-Nordheim tunnelling. The area of the cell disclosed in the '158 patent is relatively large due to the need for a separate select transistor for each storage cell site. Programming through the thin tunnel oxide utilized between the substrate and the floating gate in this cell design can also result in reliability and manufacturing problems.
U.S. Pat. Nos. 4,274,012 and 4,599,706 try to overcome the problems of the '158 patent cell by replacing the thin tunnel oxide with a relatively thick oxide between poly layers. The thick interpoly oxide layer has an enhanced electrical field due to asperities on the surface of the polycrystalline silicon floating gate, as described in the '158 patent. However, this type of device requires three layers of polycrystalline silicon and relies on much higher voltages, both of which can result in manufacturing problems.
Typical EEPROM cell operation is shown in FIG. 1. The cell is "erased" by Fowler-Nordheim tunneling of electrons from the EEPROM cell's drain D to the floating gate, raising the cell threshold voltage to a positive value. Cell "programming" is achieved by Fowler-Nordheim tunneling as well, moving electrons from the floating gate to the drain D, thereby changing the threshold voltage to a negative value. As further shown in FIG. 1, this negative programming threshold requires the use of a select transistor for "reading" the cell state. The select transistor is needed because the cell transistor conduction cannot be controlled by a gate voltage in the 0-5 V range when the cell has a negative threshold.
The operating bias conditions for the FIG. 1 EEPROM cell are provided in Table I below.
TABLE I ______________________________________ Vg, cell Vg, sel Vs, cell Vd, sel Control gate Select gate Array source Bit line ______________________________________ Erase 20 V 20 V 0 V 0 V Program 0 V 20 V Float 20 V Read 3 V 5 V 0 V 2 V ______________________________________
Various techniques for minimizing the EEPROM cell area have also been described. For example, U.S. Pat. No. 5,021,848 describes a self-aligned tunnel oxide approach. However, this cell still requires a select transistor and the process to achieve the cell structure is complicated.
Other approaches try to eliminate the select transistor. For example, U.S. Pat. No. 5,222,040 describes a method of eliminating the select transistor in an EEPROM cell by using a negative read voltage, such as -3 V. Threshold values for an EEPROM cell based on tunnel program and erase have an average value around -2 V after programming with a spread which depends on manufacturing control (typically 1-2 V). It is very likely that the threshold values for some cells will be below the read voltage despite a negative read voltage. If such is the case, then the single transistor EEPROM cell is functionality impaired. Also, high voltages in the range of 15-20 volts are required on the gates of the cell.
It should be noted that the object of the '040 patent was to produce a single transistor EEPROM cell, i.e., a cell based on tunnel programming and erase, by eliminating the need for a select transistor. U.S. Pat. No. 5,194,925 uses a triple-poly approach for achieving a single transistor cell, resulting in a complicated process.
In summary, the problem with an EEPROM cell approach, in general, is that a select transistor is invariably required, and the existing art to minimize the EEPROM cell size by eliminating the select transistor results in more complicated processes, difficult control of the separation between the read voltage and programmed negative cell threshold voltage, and the use of high gate voltages.
A flash EPROM utilizes a single transistor cell for high density memory applications. As stated above, a flash EPROM cell is programmed by hot electron injection like a conventional UV-erasable EPROM cell, and is erased by Fowler-Nordheim tunneling. By utilizing hot-electron programming rather than the Fowler-Nordheim mechanism, the threshold voltages in a flash EPROM cell are nominally positive. Due to the absence of negative threshold voltages, a select transistor is not needed, resulting in a single transistor cell. Such a cell is disclosed in U.S. Pat. No. 4,698,787.
Typical program, erase, and read conditions for a single transistor flash cell of the type disclosed in the '187 patent are given in FIGS. 2(a)-2(c). Each of FIGS. 2(a)-2(c) shows a cross-sectional view of a prior art flash EPROM cell and the bias conditions for its various operations.
For erasing the cell or cells, a large electric field is developed across the thin oxide, which is typically about 100 .ANG., between the source 25 and the floating gate 24, as illustrated in FIG. 2(a). This may be achieved by several combinations of voltage Vs on source 20 and voltage Vg on control gate 22. For example, as shown in FIG. 2(a), Vg=0 V and Vs=12 V will erase the cell by charging the floating gate 24 positive by Fowler-Nordheim tunneling, lowering the device threshold to an approximate value around 2 V (the value may be adjusted by device design). Note that the substrate 23 is at 0 V and drain 21 is floating.
An alternate erase condition may be Vg=-12 V and Vs=5 V. In this latter case, there may be modifications in the way the source 25 of the device is constructed. For example, the lightly doped n- region surrounding the source may not be required since a smaller junction breakdown voltage will suffice.
All the cells in a flash memory array can be erased together, or a subset of them can be erased at one time by choosing the appropriate method and bias conditions. As discussed above, however, the overerase problem may result in cells having negative threshold values.
The programming condition in a conventional flash EPROM cell is illustrated in the FIG. 2(b). In this case, drain 21 is taken to a voltage Vd=6 V and control gate 22 is held at a higher voltage Vg=12 V. Both source 20 and substrate 23 are held at 0 V. The resulting hot electron injection into the floating gate 24 programs the cell to a higher positive threshold, e.g., 6 V. The cells in the array that are not to be programmed can be deselected by choosing a lower Vg or Vd for these cells.
The read bias conditions for the selected cell are shown in FIG. 2(c). Drain 21 voltage Vd is at 1 V, control gate 22 voltage Vg is at 5 V, while both the source 20 and substrate 23 are held at 0 V. For an unselected cell, control gate voltage Vg is held at 0 V. This is precisely what causes the problem with overerased cells. Table II provides a summary of this type of prior art single transistor cell bias conditions. Another type of prior art single transistor cell implementation is summarized in Table III.
TABLE II ______________________________________ Vd Bitline Vg Control Gate VS Source ______________________________________ Read-select 1 V 5 V 0 V Read-desel 0 V 0 V 0 V Erase-whole array Floating 0 V 12 V Program-sel 6 V 12 V 0 V Program-desel 0 V 0 V 0 V ______________________________________
TABLE III ______________________________________ Vd Bitline Vg Control Gate VS Source ______________________________________ Read-select 1 V 5 V 0 V Read-desel 0 V 0 V 0 V Erase-select 5 V -12 V 5 V Erase-desel 5 V 0 V 5 V Program-sel 6 V 12 V 0 V Program-desel 0 V 0 V 0 V ______________________________________
The cell shown in FIGS. 2(a)-2(c) has the advantage of small cell size and simple process. However, in practice, it has been found that a few out of a large number of such cells in a flash memory application result in an "over-erase" condition, which results in a negative cell threshold voltage tail (e.g., see S. Aritome et. al., "Reliability issues of Flash Memory Cells," Proc. IEEE, vol. 81, No. 5, May 1993, pp. 776-787). This occasional erratic negative cell threshold voltage due to overerase causes problems with the functionality of the cell and has plagued the manufacturability of flash EPROMS.
Several techniques for overcoming this problem have been reported. One technique is to use a split-gate cell. A good review of the existing art can be found in U.S. Pat. No. 5,198,380. These approaches, in general, provide larger cell size than a single transistor stacked gate flash cell such as that described in the '787 patent.
Other techniques utilize additional devices or circuits. U.S. Pat. No. 5,053,990 discloses an iterative design technique to reduce overerase. U.S. Pat. No. 5,233,562 discloses a soft-disturb repair technique normally used in association with an iterative routine. U.S. Pat. No. 5,220,528 discloses a design that incorporates an extra MOS device connected to the drain. U.S. Pat. No. 5,220,533 discloses a high impedance device to limit erase. U.S. Pat. No. 5,077,691 discloses a repair technique for selectively not erasing the memory cells of a defective row by erasing on a row-by-row basis. U.S. Pat. No. 4,958,321 describes a process technique by controlling the floating poly doping to reduce overerase. All of the above methods involve varying degrees of complexity in implementation, and many of them increase the product die size significantly. In summary, while the small cell size of the flash EPROM approach provides advantages, a better solution to the overerase problem would be very desirable.
In the prior art, as described above, avoiding the overerase problem in a flash EPROM has required both device and circuit design to center the erased threshold voltage distribution at a much higher positive voltage. The distribution typically may be centered around 2 V with spread from 0.5 V to 3.5 V, (e.g., see S. Aritome et. al., Ibid). This reduces the possibility of overerased cells with negative threshold voltages. However, higher nominal values of the erased cell threshold also lead to lower cell read currents, especially with lower power supply voltage, such as 3 V. The inability of the cells in the prior art to handle larger erased cell threshold voltage spread also forces the cell design to use lower negative gate voltages for erase, which has the detrimental effect of increasing the erase time. Also, simpler non-iterative schemes reported in the literature cannot be used (e.g., see K. Yoshikawa et. al., "Comparison of current flash EEPROM erasing methods: Stability and how to control," IEDM 1992, pp. 595-598, or S. Yamada et. al., "A self-convergence erasing scheme for a simple stacked gate flash EEPROM," IEDM 1991, pp. 307-310) because, even though they provide an improvement, these schemes do not result in tight enough erased cell threshold voltage distribution and iterative routines must be used (e.g., U.S. Pat. No. 5,233,562).
Therefore, it would be highly desirable to have available a better solution for the overerase problem in flash EPROMS. Also, it would be desirable to shift the erased threshold distribution down to a smaller threshold voltage to achieve higher read current. It would also be advantageous to avoid complicated erase-verify iterative overerase repair schemes. An improved repair algorithm which will work with the proposed solution would also be useful.